There is a recurring pattern in how Nvidia gets misread as a business. The instinct — understandable, given its industry classification — is to reach for semiconductor cycle frameworks: track the capex cycle, model utilisation rates, wait for the inevitable demand correction. That framework works well for much of the chip industry. Applied to Nvidia, it has consistently produced the wrong conclusions, and the reason is structural: Nvidia stopped being a pure semiconductor company somewhere around 2012, and what replaced it is something the traditional hardware playbook was never designed to evaluate.

What Nvidia operates today is a full-stack platform ecosystem. The distinction matters enormously. A hardware company sells components into a market. A platform company creates the conditions under which customers build their own businesses — and in doing so, ties those customers to the platform in ways that are expensive, disruptive, and often impractical to unwind. Nvidia has spent two decades constructing exactly that kind of position in AI compute, layer by layer.

This piece examines the three structural layers that underpin Nvidia’s competitive durability, the strategic divergence it is now executing at the device level, and the honest set of conditions under which that durability could weaken.

Three Layers That Make the Position Stick

Nvidia’s competitive position is not the product of any single advantage. It is the compounding result of three distinct layers, each of which reinforces the others. Removing one would weaken the structure; dismantling all three simultaneously — which is what any credible challenger would need to do — is the kind of task that takes a decade, not a product cycle.

The Software Lock-In Explained

The first layer is the most structurally important, and also the most commonly underweighted in hardware-centric analyses. CUDA — Nvidia’s Compute Unified Device Architecture — is not a marketing term. It is a software platform that has been in continuous development since 2006, and it now underpins the entire ecosystem of AI development: deep learning frameworks, inference optimisation libraries, multi-GPU communication protocols, and thousands of researcher-hours of fine-tuning that are native to Nvidia silicon.

When an organisation evaluates whether to switch compute providers, the hardware price differential is only one part of the equation. The other — often larger — part is the cost of migration: rewriting existing codebases, re-validating numerical outputs, rebuilding toolchains, and absorbing the productivity loss while engineering teams develop fluency on the new stack. A 20% price advantage from a competing chip frequently disappears entirely once those costs are properly accounted for. The software layer is the moat, and CUDA is the water in it.

System Integration as a Compounding Advantage

The second layer extends the advantage beyond individual chips. With the acquisition of Mellanox in 2020 and the subsequent development of the NVLink architecture, Nvidia effectively moved up the value chain — from selling processors to selling integrated rack-scale computing systems. The GB200 NVL72, for instance, is not a collection of GPUs that happen to be in the same chassis. It is a fabric in which the interconnect, memory, networking, and compute are co-designed to minimise the bottleneck that limits real-world AI performance at scale: communication overhead between chips.

This system-level integration means that a competitor seeking to displace Nvidia cannot simply build a faster chip. They would need to match Nvidia’s chip performance, its interconnect bandwidth, its software library depth, and its system-level optimisation simultaneously. The compounding nature of these requirements is what keeps the position durable even as individual components of the hardware landscape evolve.

The Self-Reinforcing Cycle

The three layers produce a compounding cycle that becomes harder to interrupt the longer it runs:

Custom Silicon and the Limits of Vertical Integration

There is a well-established dynamic in technology infrastructure: when a supplier’s margins reach a certain level, the largest customers will eventually invest in developing their own alternatives. It is not a prediction — it is a pattern that has repeated across enterprise software, cloud infrastructure, and networking hardware. Nvidia’s data centre margins have been at the level where this dynamic reliably activates, and the hyperscale cloud providers have responded accordingly.

Google’s TPU programme, AWS’s Trainium and Inferentia chips, Meta’s MTIA, and Microsoft’s Maia are each serious, well-funded efforts. They are not in early experimentation — they are in active deployment, and their scale will increase. The question for any structural analysis is not whether they will absorb workloads that Nvidia currently handles. They will. The question is which workloads, and what the ceiling on that share shift looks like.

Projected Shift in AI Accelerator Volume

The structural reason the share shift has a ceiling is workload differentiation. AI compute is not monolithic — it splits cleanly into two categories with different performance requirements, and each category favours a different architecture.

Training a frontier model requires computational flexibility — the architecture changes frequently, the code evolves daily, and raw performance headroom matters more than efficiency. General-purpose GPUs with deep software tooling are well-suited to this. Running a trained model at scale — inference — is a different problem entirely. The model is fixed, the operations are repetitive, and the primary variable is cost-per-query. Custom silicon built for exactly that mathematical workload outperforms general-purpose GPUs on efficiency, and efficiency is what drives unit economics at hyperscale inference volumes.

The bifurcation this produces is stable rather than binary: Nvidia retains the premium, flexible, high-performance end of the market; custom ASICs absorb the high-volume, cost-sensitive, commoditised end. Both coexist, each doing what it is structurally best suited for.

The Three Conditions That Could Shift This Further

A more significant erosion of Nvidia’s position — beyond the gradual inference share shift already underway — would require at least one of three structural conditions to develop:

RTX Spark: A Calculated Hedge at the Device Edge

The RTX Spark announcement deserves more careful reading than the product launch framing it received. Jensen Huang described it as a fundamental reinvention of the personal computer — a 3nm system-on-chip combining a 20-core Arm CPU with a Blackwell-generation GPU, up to 128GB of unified memory, and approximately one petaflop of local AI compute. He positioned tokens as the new unit of value, and local AI agents running continuously as the next paradigm of personal computing.

The technology itself is genuinely significant. The strategic context, however, tells a more deliberate story than the stage narrative suggests.

“By anchoring the next generation of AI development to a CUDA-based device that sits in every developer’s bag, Nvidia extends its software ecosystem into spaces that cloud providers cannot reach.”

The cloud ASIC programmes described in Part II represent a structural constraint on Nvidia’s data centre growth over the medium term. As hyperscalers move high-volume inference workloads onto their own silicon, the portion of AI compute that runs on Nvidia hardware inside their infrastructure gradually narrows. The RTX Spark is, among other things, a strategic response to that dynamic.

If developers’ local machines become full CUDA environments — capable of running models at up to 120 billion parameters without a cloud dependency — then the CUDA ecosystem extends its reach beyond the data centre and into the device layer. Developers building for that environment are building for CUDA. The agentic AI workflows that run on those devices run on Nvidia silicon. The hyperscaler intermediary is bypassed for a meaningful category of workload.

The manufacturing economics reinforce that framing. A chip of this complexity at this memory density carries meaningful yield risk and cost floors at TSMC’s advanced nodes. This is not a product that will reach mass-market price points in its first or second generation. The addressable market — developers, researchers, high-end creators — is real but bounded. The strategic value of maintaining CUDA’s gravitational pull across a broader set of computing contexts may, over time, justify the investment even if the device business itself remains a premium niche for several years.

What the RTX Spark accomplishes structurally is this: it absorbs excess advanced packaging capacity, reduces revenue concentration in four large cloud customers, and most importantly, ensures that the agentic AI developer ecosystem of the next decade grows up on CUDA rather than on hardware Nvidia does not influence.